This invention relates to integrated circuits (xe2x80x98chipsxe2x80x99) and more particularly to large scale integrated circuits, particularly application specific integrated circuits which include various processing and data storage means and a system for recovering at least one clock signal (called hereinafter simply xe2x80x98clockxe2x80x99) from input data. One example is a chip which constitutes all or modular part of a communication unit such as a high-speed switch for a packet-based data communication system. Nevertheless, the invention is intended to have a general utility in chips which require high precision clocks.
Chips of the general nature indicated above require at least one and usually more than one clock which consists of, or should consist of, precisely regular occurring transitions between binary levels. The continued accuracy of the clock is essential for the reliable writing, reading and other processing of digital data. Owing to the increasing complexity of application specific integrated circuits and the increasing demands imposed by increasing data rates, currently in the range of gigabits per second, an application specific integrated circuit when laid out may not exhibit continually perfect clock signals. Generally, imperfections in clocks and particularly the occurrence of transitions at irregular or spurious intervals are termed xe2x80x98glitchesxe2x80x99. Such glitches may and frequently do cause unacceptable errors in the operation of the application specific integrated circuit. Accordingly it is desirable to be able to detect glitches in a clock at an early stage of manufacture.
In particular, the number and speed of flip-flops connected to any particular clock tree increases all the time. Many clocks are generated from clock recovery circuitry responsive to input signals, running at different voltage levels.
One aspect of the invention is the incorporation on a chip of a clock glitch detector. Various proposals exist for the detection of clock glitches. Early techniques employed pulse stretching and the use of a cathode ray tube, as discussed in U.S. Pat. No. 4,107,651. It is known from that patent to provide a technique which detects glitches in data but which employs for this purpose a clean sample clock synchronous to the data.
Another technique for glitch detection and intended for use within a logic analyzer is described in U.S. Pat. No. 4,353,032. This technique uses an internally generated sampling clock to sample the input data. The system will detect the existence of signals which have a duration of less than the period of the sample clock. For the detection of short glitches a high-speed clock is needed.
Various other techniques are known. It is known to multiplex the clock and known data patterns to output buffers of a chip and to use an oscilloscope device which is triggered by the glitch to provide a comparison of received and expected data patterns. This technique requires that there is enough buffer memory in a capturing device to store the data received around the time that the glitch occurs. It may not be possible to stop the triggering of the oscilloscope and accordingly the data captured by the oscilloscope at about the time of the glitch may be overwritten. Furthermore, the glitch may be too short and may be smoothed out by the capacitance of the test probes and test devices.
It is also known to multiplex the clock to an output buffer and to use a sampling oscilloscope to build a picture of the clock over time. The accuracy of this technique depends on the particular sampling scope which is used.
It has also been proposed to observe the symptoms of a clock glitch and to probe a chip. However, probing a chip is time consuming and the devices employed (such as stroboscopic scanning electron microscopes) are particularly expensive.
The present invention is based on the transmission of known data patterns repeatedly and the storage thereof in memory by means of an address generator which is clocked by the clock under investigation. The data may be written repeatedly into a set of storage locations in cyclic sequence. If a glitch occurs, a recovered data value will be clocked into two consecutive memory locations. The identity of two consecutive similar data values can be detected in real time or otherwise.
Further features of the invention will be apparent from the detailed description which follows.